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MIPI_CSI

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MIPI CSI-2 Protocol

Overview

MIPI CSI-2 (Camera Serial Interface 2) is a high-speed serial interface standard from the MIPI Alliance for connecting image sensors to application processors. It uses D-PHY or C-PHY physical layer and supports up to 4 data lanes for multi-gigabit camera data streaming.

1. Theory & Fundamentals

  • Solves: High-bandwidth image data transfer from CMOS image sensor to SoC
  • Physical layer: MIPI D-PHY — differential LVDS pairs; HS (high speed) and LP (low power) modes
  • Lanes: 1 clock lane + 1–4 data lanes
  • Speed: Up to 2.5 Gbps per lane (D-PHY v2.5), effectively 1.25 Gbps data/lane
  • Pixel formats: RAW8, RAW10, RAW12, YUV422, RGB888, etc.
  • Protocol layers: PHY → Lane Management → Packet Layer → Pixel Processing

2. Frame / Packet Structure

Long Packet:  SoP | VC(2) | DT(6) | WC(16) | ECC(8) | DATA(WC bytes) | Checksum(16) | EoP
Short Packet: SoP | VC(2) | DT(6) | DATA(16) | ECC(8) | EoP

Data Types (DT): 
  0x00 = Frame Start,  0x01 = Frame End
  0x02 = Line Start,   0x03 = Line End
  0x2A = RAW8,         0x2B = RAW10
  0x1E = YUV422 8-bit, 0x24 = RGB888

3. Protocol Mechanics

  • Virtual Channels (VC): 4 independent streams multiplexed on same physical lanes
  • Frame sync: FS (Frame Start) and FE (Frame End) short packets
  • Lane distribution: Pixel bytes distributed across data lanes in order
  • Error correction: ECC protects packet header; 16-bit checksum on data
  • LP-11 state: Both lanes HIGH in low-power mode (idle)
  • HS mode: Ultra-low swing differential signaling (200mV)

4. Hardware Implementation

  • Sensor output: D-PHY differential pairs (data + clock lanes)
  • Receiver: SoC CSI-2 receiver block (Raspberry Pi, STM32MP1, i.MX8)
  • Trace: 100Ω differential, matched length, no vias
  • Termination: 100Ω internal in receiver (D-PHY)
  • ESD: MIPI-specific ESD diodes (low capacitance)
  • Common sensors: OV5640, IMX219, IMX477, AR0234

5. Register-Level / Configuration

// Typically via Linux V4L2 / device tree or vendor SDK
// Embedded bare-metal: Use SoC CSI peripheral registers

// Example: Enable CSI receiver on i.MX6 (simplified)
CSI_CR1 = CSI_MCLKDIV(4) | CSI_FCC | CSI_GCLK_MODE; // Configure pixel clock
CSI_CR3 = 0; // Clear control register
CSI_CR1 |= CSI_EN; // Enable CSI

// Most systems use driver frameworks (V4L2 on Linux, ISP SDK on DSPs)

6. Driver / Software Development

// Using Raspberry Pi / Linux V4L2 (common embedded approach)
int fd = open("/dev/video0", O_RDWR);
struct v4l2_format fmt = {.type = V4L2_BUF_TYPE_VIDEO_CAPTURE};
fmt.fmt.pix.width = 1920; fmt.fmt.pix.height = 1080;
fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_YUYV;
ioctl(fd, VIDIOC_S_FMT, &fmt);

// Request buffers, mmap, start streaming, capture frames

7. Debugging & Testing

  • Specialized MIPI CSI-2 analyzers (Aldec, Introspect Systems, Keysight)
  • Check LP-11 idle state before HS burst
  • Scope: Differential probe on data/clock lanes, verify HS eye diagram
  • Common issues: Lane count mismatch; incorrect pixel format; sensor I2C config wrong
  • v4l2-ctl tool on Linux for format and capture testing

8. Real-World Applications

  1. Smartphone front/rear cameras (primary use case)
  2. Automotive cameras (ADAS, backup cameras)
  3. Drone FPV cameras
  4. Industrial machine vision cameras
  5. Medical endoscopes and surgical cameras

9. Advanced Topics & Edge Cases

  • DPHY vs CPHY: C-PHY uses 3-wire tri-state signaling, higher BW per pin
  • Embedded ISP: Sensor RAW data processed by hardware ISP pipeline
  • Multi-camera sync: Frame sync between multiple sensors
  • MIPI CSI-3: UniPro-based, used in high-end mobile
  • Lane merging: 4-lane 4K at 60fps requires full 4-lane operation

10. Standards & Variants

Standard PHY Speed/lane Notes
CSI-2 v1.3 D-PHY 1 Gbps Most common
CSI-2 v2.0 D-PHY v2.0 2.5 Gbps Latest mobile
CSI-2 v2.0 C-PHY 2.5 Gsps Higher density
CSI-3 M-PHY 6 Gbps High-end mobile

💡 Practical Examples

Example 1: Configure OV5640 for 1080p

// Send I2C commands to OV5640 to configure 1920x1080 30fps
OV5640_WriteReg(0x3800, 0x01); // HREF start MSB
// ... (hundreds of register writes from sensor driver table)

Example 2: Capture frame on Raspberry Pi

raspistill -o image.jpg -w 1920 -h 1080
v4l2-ctl --device /dev/video0 --stream-mmap --stream-count 10

Example 3: RAW10 to RGB conversion

// Each pixel is 10 bits, packed 4 pixels in 5 bytes
// Bayer pattern demosaicing required for color output

🧪 Practice Questions

Beginner

  1. What does CSI stand for?
  2. How many virtual channels does MIPI CSI-2 support?
  3. What is the purpose of the ECC in CSI-2 packets?
  4. What physical layer does CSI-2 typically use?
  5. Name 2 common image sensors that use CSI-2.

Intermediate

  1. Explain LP and HS states in MIPI D-PHY.
  2. What is a virtual channel and when is it useful?
  3. How is RAW10 pixel data packed in CSI-2 packets?
  4. What is the maximum bandwidth of 4-lane CSI-2 at 1Gbps/lane?
  5. How does CSI-2 handle frame synchronization?

Advanced

  1. Design a 4K 60fps camera interface using MIPI CSI-2 with 4 lanes.
  2. Implement a Linux V4L2 sensor driver for a custom image sensor.
  3. How would you synchronize two CSI-2 cameras for stereo vision?
  4. Analyze a CSI-2 capture failure using a protocol analyzer.
  5. Compare D-PHY and C-PHY for a 12MP sensor interface.

Hands-on Projects

  1. Raspberry Pi Camera: Stream MIPI CSI-2 video, apply OpenCV processing.
  2. Custom Sensor Driver: Write Linux V4L2 driver for OV5640.
  3. Multi-Camera System: Sync 2 CSI-2 cameras for 3D depth sensing.

Checklist

  • [ ] Explain CSI-2 packet structure and data types
  • [ ] Configure sensor I2C registers for target resolution/format
  • [ ] Set up CSI-2 receiver on target SoC
  • [ ] Capture frames using V4L2 or bare-metal DMA
  • [ ] Verify with MIPI protocol analyzer
  • [ ] Handle RAW Bayer data and demosaicing
  • [ ] Implement virtual channel multiplexing
  • [ ] Optimize for minimum latency capture
  • [ ] Write Linux V4L2 subdevice driver
  • [ ] Design PCB for CSI-2 interface
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